In conventional integrated circuit technology, interconnections are made using wire bond pads arranged in one or more rows around the periphery of the semiconductor die, or using solder bump pads arranged in an array over the circuit area of the die. The trend in the electronics industry is to increase reliance on solder bump connections. Often, existing circuit designs that originally utilized wire bonding are retrofitted for solder bumps or are made with the solder bumps as an option in addition to the conventional wire bonding assembly.
Together with the provided wire bond pads, there is circuitry that protects the interior parts of the circuit from electrostatic discharge (ESD) events, for example that can occur during handling of the circuit die. ESD can result in a voltage peak of about 2,000 volts or more, which can result in a discharge of a current of about 1.5 amperes over a resistance of about 1,500 ohms. The protective ESD circuits are typically located between the input/output (I/O) bond pads around the periphery of the die and the transistor gates or other electronic components to which the pads are electrically connected. The ESD circuits provide a path from the I/O pads to a ground pad, or to a power or bias voltage path for the die. This electrical path is designed to be actuated by a high voltage, such as an electrostatic discharge, that occurs at for instance input or output pads of a die.
Generally, the ESD structures are configured in a ring placed near the edge of the circuit and in situ with the peripheral bond pads. This allows the signal path from the circuit edge to the ESD to be made sufficiently short and strong. When such semiconductor dice are also provided with bump pads for use in flip-chip configuration, bump pads distributed over the interior area are routed to the ESD ring, resulting in long interconnect lengths and often complex routing that can take up die area.